Wiki source code of Trigger Howto

Version 16.1 by sndueste on 2020/01/21 13:02
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sendels 1.1 1
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sndueste 6.1 3 {{toc/}}
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sndueste 10.1 5 = Introduction (user panel)
6 =
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grunewal 14.1 8 The MTCA based triggers have a jitter in the few ps range, the delay can be shifted in 1 ns steps (over many ms), one can choose between 10 Hz triggers, frequencies locked to the pulses (e.g. 1MHz) and the actual bunch patterns. A detailed description can be found in [[x2Timer manual>>attach:x2Timer.pdf]] ([[Design Paper>>url:http://ttfinfo2.desy.de/doocs/Timing/CDRv2.2short.pdf||shape="rect"]]).
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sndueste 6.1 10 in short: the triggers are for low impedance (~~50 OHM terminated ?? ), 5V triggers with an adjustable width. The main control panel for the x2 timer has the control options for the 3 front modules (connected with a RJ45 cable - connecting to a "trigger box" with 2 trigger exits (Lemo) each) and 8 Lemo exits at the back of the crate. in the BL-beamline case these triggers are connected to the BNC (patch panel) ports at the rack.
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grunewal 14.1 12 The main control can be done with a simplified user panel which can handle the timing in respect to the FEL pulses and not in respect to some (arbitrary) reference time ( Event)
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grunewal 14.1 14 [[image:attach:Trigger_scheme.gif]]
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sndueste 10.1 17 = Different trigger events (starting points) =
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sndueste 6.1 19 one can configure each channel for an individual trigger event
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21 **FLASH1**
22
sendels 2.1 23 (% class="wrapped" %)
sendels 1.1 24 |(((
25 trigger No
26 )))|(((
27 function
28 )))
29 |(((
30 16
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32 the MCA trigger 3.11 ms before the Flash1 pulses (same as A6 but more stable)
33 )))
34 |(((
35 166
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37 A6 event. still possible to use but less precise than 16
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40 162
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42 A2 event as earliest ( 24 ms before the FEL)
43 )))
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45 224
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47 E0 event of the BL fast shutter ( 19 ms before the FEL)
48 )))
49 |(((
50 225
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52 E1 event of the PG fast shutter ( 19 ms before the FEL)
53 )))
54 |(((
55 21
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57 Trig16 + first bunch of FLASH1 - this trigger is shifted when FL1 starts later than "700"
58 )))
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64 **FLASH2**
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sendels 2.1 66 (% class="wrapped" %)
sendels 1.1 67 |(((
68 trigger No
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70 function
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73 22
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75 Trig116 + first bunch of FLASH2 - this trigger is shifted when FL2 starts at a different start time
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78 181
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sndueste 6.1 80 shifts with the start time of FLASH2 as event 22 but comes 22 ms ! before the FEL
sendels 1.1 81 )))
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sndueste 5.1 83 from this trigger as starting point one can shift the timing in 9 ns steps first and finally in 0.9 ns steps for fine adjustment.
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sndueste 6.1 85 \\
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sndueste 6.1 87 = Expert panels =
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sndueste 6.1 91 [[image:attach:image2019-9-17_13-10-56.png||height="250"]] [[image:attach:image2019-9-17_13-8-46.png||height="400"]]
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sndueste 7.1 93 With the **"Expert overview"** one gets the overview over all channels available on the timing card and can configure the card. This is useful to look what channels are using clock settings or burst mode settings that one wants to change ... and using the other tabs one can set parameters for clocks and bursts (see below)
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sndueste 7.1 97 For each trigger channel there is in addition an **"Expert panel"** to set the properties of THIS channel
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99 [[image:attach:image2019-9-17_13-14-52.png||height="250"]] [[image:attach:image2019-9-17_13-15-38.png||width="550"]]
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sndueste 10.1 105 = Set a constant frequency to a channel =
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107 =
sndueste 6.1 108 [[image:attach:image2019-9-17_13-18-9.png||height="250"]][[image:attach:image2019-9-17_13-18-37.png||height="149"]] =
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sndueste 7.1 112 The timer card provides the option to generate  frequencies that are synched to the FEL reprate on the ps level. One can set 3 Clocks by deviding the reference frequency of 54.2 MHz by n.** Please check (using the Expert overview ) before changing a frequency of it is used for some other channel !!**
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114 Since our main FEL frequency is 100.31 MHz the dividers are not straight forward:
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sndueste 10.1 116 [[image:attach:image2019-9-17_14-22-29.png||width="450" align="right"]]
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sndueste 7.1 120 (% class="wrapped" %)
sndueste 6.1 121 |=(((
122 Clock frequency
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sndueste 7.1 124 Divider to be set
sndueste 6.1 125 )))
126 |(((
127 "1 MHz" (1000.31 kHz)
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129 53
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sndueste 7.1 132 "500 kHz" (501.5 kHz)
sndueste 6.1 133 )))|(((
sndueste 7.1 134 107
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136 |(((
sndueste 7.1 137 "250 kHz" (250.8 kHz)
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sndueste 7.1 139 215
sndueste 6.1 140 )))
sndueste 7.1 141 |(% colspan="1" %)(((
142 "200 kHz" (200.6 kHz)
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144 269
145 )))
146 |(% colspan="1" %)(((
147 "100 kHz" (100.3 kHz)
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149 539
150 )))
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sndueste 15.1 154 == General FLASH frequencies: ==
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sndueste 16.1 158 (% class="relative-table wrapped" style="width: 19.422%;" %)
sndueste 15.1 159 |(((
160 (% style="color: rgb(0,0,255);" %)Name
161 )))|(((
162 (% style="color: rgb(0,0,255);" %)Frequency
163 )))|(((
164 (% style="color: rgb(0,0,255);" %)Divider
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166 |(((
167 1.3 GHz
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169 1300.000000 MHz
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sndueste 15.1 172 )))
173 |(((
174 108 MHz
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176 108.333333 MHz
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178 12
179 )))
180 |(((
181 9 MHz
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183 9.02777777 MHz
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185 144
186 )))
187 |(((
188 4.5 MHz
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190 4.513888 MHz
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192 288
193 )))
194 |(((
195 1 MHz
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197 1.003086 MHz
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199 1296
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sndueste 7.1 204 Once a clock is configured with the right frequency one can choose in the "expert panel" of the according channel the "FPGA clock" in the "input source select"  chooser.
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sndueste 10.1 206 One has to set the delay to values less than the repetition rate ... (so for 1 MHz between 0 and 990 µs)  and the trigger width also less than the rep rate ...
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sndueste 15.1 208 This results in a continuous train of pulses with the set trigger width.
sndueste 8.1 209
sndueste 10.1 210 = Creating an (own) burst trigger =
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212 One can use now a SECOND trigger channel which is set to a regular 10 Hz trigger  and gate the clock output to create a burst with defined start point and length,
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sndueste 11.1 214 For the example we use the FRONT.TRG2 (BL3 Trg5) as gate pulse which defines the length of the burst (set with the trigger width) and the (rough) starting point of the burst. This trigger is only used as gate and the physical trigger output is NOT used.
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sndueste 11.1 216 The  second channel (here FRONT.TRG3 (BL3 Trg6) which is set to the clock frequency defines the reprate (by the FPGA clock setting) , the exact starting point of the first trigger ( by the delay ) and the width of the  MHz/kHz triggers (width).
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sndueste 11.1 218 **To get from the clock to the burst trigger** one has to:
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sndueste 11.1 220 * set the  "2nd source select" to the gate trigger ( here FRONT.TRG2) - this defines a second source to considder for the trigger output.
221 * and the "output source select" to "AND 2nd Ch."  this finally only sends a trigger if on both inputs (clock and gate) we have a high signal.
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sndueste 11.1 225 [[image:attach:image2019-9-17_14-35-5.png||height="250"]] [[image:attach:image2019-9-17_14-34-38.png||width="400"]]
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sndueste 11.1 231 = Real bunch trigger  - get a trigger for each FEL pulse =
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sndueste 11.1 235 Sometimes it is convenient to get a trigger pulse for each pulse in the FEL. thus if the FEL number of bunches or reprate are changed, the trigger adapts accordingly.
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sndueste 11.1 237 For this one has to select the source of interest in the expert overview panel (tab: "Bunch pattern") ... well for us this is FLASH1 (FL1D) or FLASH2 (FL2D)
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sndueste 11.1 239 There are 6 different bunch pattern "channels" one can configure. Typically only 2 are needed ... And in each one there are 6 selectors to choose sources . We only need one - it does not matter in which one is used.
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sndueste 12.1 241 [[~[~[image:attach:image2019-9-17_14-51-28.png~|~|height="250"~]~]>>attach:image2019-9-17_14-51-28.png]][[image:attach:image2019-9-17_14-47-15.png||thumbnail="true" height="199"]]
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sndueste 11.1 245 In the expert panel one can now choose the configured "Bunch Pattern" as "Input source select"
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sndueste 11.1 247 **NOTE: To shift the burst in time one can no longer use the delay of the individual channel BUT the delay in the "Bunch pattern" tab in the expert overview! This now shifts all bursts ... so you better know what you are doing. typically the burst is already shifted to the actual FEL timing ... Shifting the timing should be discussed with the beamline scientist / local contact ...**
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sndueste 13.1 251 [[image:attach:image2019-9-17_15-4-47.png||height="250"]][[image:attach:image2019-9-17_14-52-40.png||height="250"]]
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