Wiki source code of Trigger Howto

Version 16.1 by sndueste on 2020/01/21 13:02

Show last authors
1
2
3 {{toc/}}
4
5 = Introduction (user panel)
6 =
7
8 The MTCA based triggers have a jitter in the few ps range, the delay can be shifted in 1 ns steps (over many ms), one can choose between 10 Hz triggers, frequencies locked to the pulses (e.g. 1MHz) and the actual bunch patterns. A detailed description can be found in [[x2Timer manual>>attach:x2Timer.pdf]] ([[Design Paper>>url:http://ttfinfo2.desy.de/doocs/Timing/CDRv2.2short.pdf||shape="rect"]]).
9
10 in short: the triggers are for low impedance (~~50 OHM terminated ?? ), 5V triggers with an adjustable width. The main control panel for the x2 timer has the control options for the 3 front modules (connected with a RJ45 cable - connecting to a "trigger box" with 2 trigger exits (Lemo) each) and 8 Lemo exits at the back of the crate. in the BL-beamline case these triggers are connected to the BNC (patch panel) ports at the rack.
11
12 The main control can be done with a simplified user panel which can handle the timing in respect to the FEL pulses and not in respect to some (arbitrary) reference time ( Event)
13
14 [[image:attach:Trigger_scheme.gif]]
15 \\
16
17 = Different trigger events (starting points) =
18
19 one can configure each channel for an individual trigger event
20
21 **FLASH1**
22
23 (% class="wrapped" %)
24 |(((
25 trigger No
26 )))|(((
27 function
28 )))
29 |(((
30 16
31 )))|(((
32 the MCA trigger 3.11 ms before the Flash1 pulses (same as A6 but more stable)
33 )))
34 |(((
35 166
36 )))|(((
37 A6 event. still possible to use but less precise than 16
38 )))
39 |(((
40 162
41 )))|(((
42 A2 event as earliest ( 24 ms before the FEL)
43 )))
44 |(((
45 224
46 )))|(((
47 E0 event of the BL fast shutter ( 19 ms before the FEL)
48 )))
49 |(((
50 225
51 )))|(((
52 E1 event of the PG fast shutter ( 19 ms before the FEL)
53 )))
54 |(((
55 21
56 )))|(((
57 Trig16 + first bunch of FLASH1 - this trigger is shifted when FL1 starts later than "700"
58 )))
59
60 \\
61
62 \\
63
64 **FLASH2**
65
66 (% class="wrapped" %)
67 |(((
68 trigger No
69 )))|(((
70 function
71 )))
72 |(((
73 22
74 )))|(((
75 Trig116 + first bunch of FLASH2 - this trigger is shifted when FL2 starts at a different start time
76 )))
77 |(((
78 181
79 )))|(((
80 shifts with the start time of FLASH2 as event 22 but comes 22 ms ! before the FEL
81 )))
82
83 from this trigger as starting point one can shift the timing in 9 ns steps first and finally in 0.9 ns steps for fine adjustment.
84
85 \\
86
87 = Expert panels =
88
89 \\
90
91 [[image:attach:image2019-9-17_13-10-56.png||height="250"]] [[image:attach:image2019-9-17_13-8-46.png||height="400"]]
92
93 With the **"Expert overview"** one gets the overview over all channels available on the timing card and can configure the card. This is useful to look what channels are using clock settings or burst mode settings that one wants to change ... and using the other tabs one can set parameters for clocks and bursts (see below)
94
95 \\
96
97 For each trigger channel there is in addition an **"Expert panel"** to set the properties of THIS channel
98
99 [[image:attach:image2019-9-17_13-14-52.png||height="250"]] [[image:attach:image2019-9-17_13-15-38.png||width="550"]]
100
101 \\
102
103 \\
104
105 = Set a constant frequency to a channel =
106
107 =
108 [[image:attach:image2019-9-17_13-18-9.png||height="250"]][[image:attach:image2019-9-17_13-18-37.png||height="149"]] =
109
110 \\
111
112 The timer card provides the option to generate  frequencies that are synched to the FEL reprate on the ps level. One can set 3 Clocks by deviding the reference frequency of 54.2 MHz by n.** Please check (using the Expert overview ) before changing a frequency of it is used for some other channel !!**
113
114 Since our main FEL frequency is 100.31 MHz the dividers are not straight forward:
115
116 [[image:attach:image2019-9-17_14-22-29.png||width="450" align="right"]]
117
118 \\
119
120 (% class="wrapped" %)
121 |=(((
122 Clock frequency
123 )))|=(((
124 Divider to be set
125 )))
126 |(((
127 "1 MHz" (1000.31 kHz)
128 )))|(((
129 53
130 )))
131 |(((
132 "500 kHz" (501.5 kHz)
133 )))|(((
134 107
135 )))
136 |(((
137 "250 kHz" (250.8 kHz)
138 )))|(((
139 215
140 )))
141 |(% colspan="1" %)(((
142 "200 kHz" (200.6 kHz)
143 )))|(% colspan="1" %)(((
144 269
145 )))
146 |(% colspan="1" %)(((
147 "100 kHz" (100.3 kHz)
148 )))|(% colspan="1" %)(((
149 539
150 )))
151
152 \\
153
154 == General FLASH frequencies: ==
155
156 \\
157
158 (% class="relative-table wrapped" style="width: 19.422%;" %)
159 |(((
160 (% style="color: rgb(0,0,255);" %)Name
161 )))|(((
162 (% style="color: rgb(0,0,255);" %)Frequency
163 )))|(((
164 (% style="color: rgb(0,0,255);" %)Divider
165 )))
166 |(((
167 1.3 GHz
168 )))|(((
169 1300.000000 MHz
170 )))|(((
171 \\
172 )))
173 |(((
174 108 MHz
175 )))|(((
176 108.333333 MHz
177 )))|(((
178 12
179 )))
180 |(((
181 9 MHz
182 )))|(((
183 9.02777777 MHz
184 )))|(((
185 144
186 )))
187 |(((
188 4.5 MHz
189 )))|(((
190 4.513888 MHz
191 )))|(((
192 288
193 )))
194 |(((
195 1 MHz
196 )))|(((
197 1.003086 MHz
198 )))|(((
199 1296
200 )))
201
202 \\
203
204 Once a clock is configured with the right frequency one can choose in the "expert panel" of the according channel the "FPGA clock" in the "input source select"  chooser.
205
206 One has to set the delay to values less than the repetition rate ... (so for 1 MHz between 0 and 990 µs)  and the trigger width also less than the rep rate ...
207
208 This results in a continuous train of pulses with the set trigger width.
209
210 = Creating an (own) burst trigger =
211
212 One can use now a SECOND trigger channel which is set to a regular 10 Hz trigger  and gate the clock output to create a burst with defined start point and length,
213
214 For the example we use the FRONT.TRG2 (BL3 Trg5) as gate pulse which defines the length of the burst (set with the trigger width) and the (rough) starting point of the burst. This trigger is only used as gate and the physical trigger output is NOT used.
215
216 The  second channel (here FRONT.TRG3 (BL3 Trg6) which is set to the clock frequency defines the reprate (by the FPGA clock setting) , the exact starting point of the first trigger ( by the delay ) and the width of the  MHz/kHz triggers (width).
217
218 **To get from the clock to the burst trigger** one has to:
219
220 * set the  "2nd source select" to the gate trigger ( here FRONT.TRG2) - this defines a second source to considder for the trigger output.
221 * and the "output source select" to "AND 2nd Ch."  this finally only sends a trigger if on both inputs (clock and gate) we have a high signal.
222
223 \\
224
225 [[image:attach:image2019-9-17_14-35-5.png||height="250"]] [[image:attach:image2019-9-17_14-34-38.png||width="400"]]
226
227 \\
228
229 \\
230
231 = Real bunch trigger  - get a trigger for each FEL pulse =
232
233 \\
234
235 Sometimes it is convenient to get a trigger pulse for each pulse in the FEL. thus if the FEL number of bunches or reprate are changed, the trigger adapts accordingly.
236
237 For this one has to select the source of interest in the expert overview panel (tab: "Bunch pattern") ... well for us this is FLASH1 (FL1D) or FLASH2 (FL2D)
238
239 There are 6 different bunch pattern "channels" one can configure. Typically only 2 are needed ... And in each one there are 6 selectors to choose sources . We only need one - it does not matter in which one is used.
240
241 [[~[~[image:attach:image2019-9-17_14-51-28.png~|~|height="250"~]~]>>attach:image2019-9-17_14-51-28.png]][[image:attach:image2019-9-17_14-47-15.png||thumbnail="true" height="199"]]
242
243 \\
244
245 In the expert panel one can now choose the configured "Bunch Pattern" as "Input source select"
246
247 **NOTE: To shift the burst in time one can no longer use the delay of the individual channel BUT the delay in the "Bunch pattern" tab in the expert overview! This now shifts all bursts ... so you better know what you are doing. typically the burst is already shifted to the actual FEL timing ... Shifting the timing should be discussed with the beamline scientist / local contact ...**
248
249 \\
250
251 [[image:attach:image2019-9-17_15-4-47.png||height="250"]][[image:attach:image2019-9-17_14-52-40.png||height="250"]]
252
253 \\
254
255 \\
256
257 \\
258
259 \\
260
261 \\
262
263 \\
264
265 \\
266
267 \\